The present invention relates to a semiconductor design technology; and, more particularly, to an internal voltage generator capable of supplying a stable internal voltage regardless of an unstable external voltage.
An internal voltage generator, which is used as a power source in a semiconductor memory device, supplies internal voltages in different levels using an external supply. Particularly, as the trend of low voltage and low power consumption is getting increased in the semiconductor memory device, the internal voltage generator is employed in dynamic random access memories recently. Meanwhile, since a voltage required to drive a circuit is produced in the device itself, many efforts are made to produce internal voltages which have a stable level regardless of the changes of the ambient temperature, the process, the pressure and so on.
FIG. 1 is a block diagram illustrating a conventional internal voltage generator. Referring to FIG. 1, the conventional internal voltage generator includes a level detecting unit 10 for detecting a level of a high voltage VPP, an oscillator 20 for producing a periodical signal OSC in response to a detecting signal DT_EN from the level detecting unit 10, and a charge pumping unit 30 for producing the high voltage VPP, which is higher than the external supply voltage VDD, by pumping charges from an external supply voltage VDD in response to the periodical signal OSC.
As described above, the conventional internal voltage generator produces the periodical signal OSC by driving an output signal of the oscillator 20 after detecting the voltage level drop of the high voltage VPP via the level detecting unit 10. Also, the charge pumping unit 30 is activated during the activation of the periodical signal OSC and maintains a predetermined level of the high voltage VPP.
Referring to FIG. 2, the oscillator 20 in the conventional internal voltage generator includes a NAND gate ND1 for NANDing a detecting signal and the periodical signal OSC, and a delay unit 22 for outputting the signal OSC by delaying an output signal of the NAND gate ND1. That is, the oscillator 20 produces the periodical signal OSC which has a half period of time through the NAND gate ND1 and the delay unit 22 at the time of the activation of the detecting signal.
FIG. 3 is a circuit diagram illustrating the charge pumping unit 30 of FIG. 1. Referring to FIG. 3, the charge pumping unit 30 includes an inverter I7 for inverting the periodical signal OSC, a capacitor C1 for storing electric charges in an output terminal of the inverter I7, a PMOS transistor PM1 for driving a supply terminal for the high voltage VPP in response to the external voltage VDD, and a capacitor C2, which is connected to the supply terminal for the high voltage VPP, for storing the electric charges.
As described above, the charge pumping unit 30 includes the capacitors C1 and C2 and the PMOS transistor PM1. Meanwhile, the driving of the conventional internal voltage generator will be illustrated briefly referring to FIGS. 1 and 2. First, the detecting signal is activated by the level detecting unit 10 in case where the level of the high voltage VPP is lower than the target value. Subsequently, the oscillator 20 produces the periodical signal OSC having a predetermined period of time while the detecting signal is activated.
The external voltage VDD is stored in the capacitor C1 in the charge pumping unit 30 and initialized. Subsequently, if the periodical signal OSC transits to a high level, the PMOS transistor PM1 is turned off and the high voltage VPP of 0V is outputted. Subsequently, if the periodical signal OSC transits to a low level, the PMOS transistor PM1 is turned on so that a voltage level of 2×VDD, which is taken by the external voltage VDD and the capacitor C1, is applied to the supply terminal of the high voltage VPP. At this time, the high voltage VPP of 2×VDD is also stored in the capacitor of the supply terminal.
The driving operations, as described above, are repeatedly performed such that the high voltage VPP which is higher than the external voltage VDD level from the input power source is supplied. In this way, the charge pumping unit 30 essentially conducts the operation mode to store the electric charges in a capacitor through the level swing of the external voltage VDD. Therefore, the pumped current amount increases linearly with the increase of the power supply voltage.
On the other hand, in the conventional charge pumping unit, there is a problem in that the supplied high voltage VPP is also increased when the external voltage VDD is increased. The reason why the supplied high voltage VPP is increased is that the driving of the level detecting unit is not fast although the external voltage VDD is increased. In other words, the switching current of the charge pumping unit increases and the period of the periodical signal OSC is short when the external voltage VDD is increased. Therefore, as the external voltage VDD is increased, an amount of the current pumped by the charge pumping unit is exponentially increased such that the charges stored in the capacitor are accumulated with the increase of the high voltage VPP. However, as described above, since the driving of the level detecting unit is not fast in compliance with the increase of the accumulated high voltage VPP, the increased voltage level is detected by the level detecting unit after the high voltage VPP has been already increased. That is, the supplied high voltage VPP is increased over a target value due to the increase of the external voltage VDD. Furthermore, the unstable level of the high voltage VPP can deteriorate the reliability of the semiconductor memory device.